Real-life physical systems are frequently designed with the aid of graphical computer models. The designer attempts to design the graphical model so that it represents the attributes and functionality of the system being designed. Once the designer is satisfied with the design of the graphical model, the graphical model frequently serves as the basis for code generation in a target language with the code being used to construct the physical system represented by the graphical model. An example of this process is the conversion of graphical models into VHDL, Verilog and other hardware description languages during the design of integrated circuits. The graphical model may first be converted into an intermediate representation (IR) of the graphical model before being converted into the target language.
Unfortunately, the conversion of graphical models directly into a target language, with or without first converting the graphical model into an IR, suffers from a number of drawbacks. It is frequently desirable to simulate the performance of the system before building the physical model. HDL (hardware description language) simulations and other target language simulations tend to run more slowly and require more resources than simulations in a graphical programming environment. Additionally, if an IR is being used to translate the graphical model into a target language, it would be desirable to validate the translation of the graphical model into the IR and simulate a graphical model based on the IR to make sure no undesirable behavioral changes have been introduced to the model during the translation process.